1. Field of Invention
The present invention relates to the field of central processing units in microcomputers in which data is transferred between a central processing unit and a multiple of peripherals including input/output devices and memories.
2. Description of the Prior Art
A typical computer system, such as marketed by Intel Corporation under the trademark, Intel 8080, since at least 1975, consists of a central processor unit (CPU), a memory, and input/output devices. (A copy of a user's manual describing the Intel 8080 having been deposited and made of record herein as an attachment to the application). The memory stores instructions and data. The program, formed by a group of logically related instructions, is stored in the memory. The CPU reads each instruction in sequence or as directed by the program. Based upon the content of the instruction, the CPU will obediently perform the specified operations which may include internal data processing with the CPU and bidirectional transfer of digital information between the CPU, the memory and the input/output devices or ports. The CPU may be combined with a plurality of external masters to cooperate on a system level to execute system instructions. External masters are defined as any external circuit which may use the external busses which are also used by the CPU. These external masters include external CPUs, computers, and bus control circuits, such as direct memory access (DMA) controllers such as the circuit marketed under the trademark Intel 8257, or interrupt controllers such as the circuit marketed under the trademark Intel 8259.
The activities of the central processor are cyclical. The processor fetches an instruction, performs the operations required, fetches the next instruction and so forth. An instruction fetch is merely a special memory read operation that brings the instruction to the CPU's instruction register. The instruction fetch may then call for data to be read from the memory to the CPU. The CPU again issues a "read" signal and transmits the proper memory address to the memory. The memory responds by returning the requested word. The data received is placed in the accumulator or one of the other general purpose registers within the CPU. A memory write operation is similar to a "read" except for the direction of data flow. The CPU issues a "write" signal, sends the proper memory address, and then sends the data word to be written into the addressed memory location. Input and output operations are similar to memory read and write operations with the exception that a peripheral input/output device is addressed instead of a memory location. The CPU issues the appropriate input or output control signal, sends the proper device address and either receives the data being input or sends the data to be output.
Clearly, the coordination and timing of instructions and data transfers between input and output devices, the memory and the CPU is critical and may be complex. Furthermore, large areas of chip space within integrated circuit CPU, input and output devices, and memories are consumed by coupling with external bus terminals. Therefore, it would be advantageous if a computer system could be designed which would reduce the number of bidirectional information bus lines and terminals, and institute a simplified data transfer protocol between the CPU and the peripherals without sacrificing the capacity, speed, and flexibility of data flow within the computer system.